18 mars 2013 ~ 0 Commentaire

13 January 2013 BFL ASIC UPDATE

Hello everyone. It’s been about a month since our last update and it’s high time we had another, since we have lots of information to share this time around.

To start off with, our chip production is going well. I am traveling to our packaging facility in California on Wednesday the 16th of January to do a walk through with the lead developer on our ButterflyLabs ASIC team as well as speak with some of the engineers to make sure everyone is on the same page. We have confirmed with the fab directly (not through any intermediaries) that our chips will be done no later than the 31st of January and ready for delivery. I will be at the foundry prior to that date to speak with some of the engineers and accept delivery of a portion of the chips to hand deliver to our packaging facility. This means our delivery date is expected the week of the 10th of February. We know it’s not the end of October and we want to deeply apologize for the delays. However, I think that once you get to the end of this post many people will understand why we’ve been delayed and hopefully how it will ultimately benefit all of our customers a great deal. So please, read on! 13 January 2013 BFL ASIC UPDATE smile

So, I know the question first and foremost on everyone’s mind (besides when we are shipping) is « Why are we delayed so long? »

Several things have happened to push us out from our target date… most things have been minor, but they have added up and I have detailed many of them in previous updates and on various threads throughout the forums. However, the biggest delay we’ve incurred has been twofold:

  1. We absolutely, positively want to ship a chip that works perfectly. We don’t want to send a chip that has problem or limitations. To that end, we have made some optimizations to the final layers of silicon that we feel will benefit everyone going forward due to point two:
  2. The biggest single reason for the delay is due to a package change.

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